1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the present invention relates to a MOS transistor having a trench, which enhances driving performance with a use of a buried layer.
2. Description of the Related Art
A MOS transistor is a device locating at the core of electronic components, and hence downsizing, reduction of power consumption, and driving performance enhancement of the MOS transistor are important issues. As a method of enhancing the driving performance of the MOS transistor, there is given a method involving making a gate width larger, to thereby decrease the on-resistance. Enlargement of the gate width, however, causes a problem in that an occupation area of the MOS transistor becomes larger. In view of the problem, there has been proposed until now a technology in which the gate width may be made larger, while suppressing the increase of the occupation area of the MOS transistor with a use of a trench.
With reference to FIGS. 4A to 4D, a conventional semiconductor device is described.
As illustrated in a perspective view of FIG. 4A, there is provided a trench 13 in a width direction (W direction) of a MOS transistor, in which a length of an effective gate width is larger than a width of a gate electrode 15 on a surface, whereby an on-resistance per unit area may be reduced without reducing a withstanding voltage of the MOS transistor.
FIG. 4B is a schematic plan view of the MOS transistor. A cross section of the trench 13 denoted by A-A′ and a cross section of a region without the trench 13 denoted by B-B′ are illustrated in FIG. 4D and FIG. 4C, respectively. A region illustrated in FIG. 4C becomes a normal planer MOS transistor, and hence, when a current flows from a high concentration source diffusion layer 16 to a high concentration drain diffusion layer 17, a current path is as illustrated in FIG. 4C with an arrow A. On the other hand, in the region having the trench 13, which is illustrated in FIG. 4D, the current is obtained on a side surface parallel to the sheet in the MOS transistor width direction as illustrated with an arrow B and on a bottom portion as illustrated with an arrow C. (For example, see JP 2006-49826 A.)
However, in the conventional technology, in a case where a length of a transistor L is reduced so as to achieve more enhanced driving performance, a distance difference in effective channel length is markedly observed. In the path C of FIG. 4D and the path A of FIG. 4C, a plane region illustrated as the path A is predominant, and a current hardly flows in the bottom portion C. Accordingly, there arises a problem in that, even when the trench 13 is deeply formed and the length of an effective gate width is enlarged, to thereby reduce an on-resistance, the driving performance cannot be obtained. In addition, since a gate length (L direction) of the transistor cannot be reduced, there occurs a disturbance in which the area cannot be reduced.
As described above, in the structure of FIG. 4A, even when a trench depth is made larger or the gate width (W direction) is reduced to make the effective gate width longer, the gate length (L length direction) cannot be reduced. Accordingly, there arises a problem in that the driving performance can be obtained no more than expected, or a problem in that the area of the transistor cannot be reduced. This is because a difference in effective channel length among a top surface, a side surface, and a bottom surface of the trench is markedly observed owing to the reduction of the L length, a current is likely to flow preferentially on the top surface of the trench, and the current flowing on a bottom surface, which is a feature of the provision of the trench, reduces.